(1) Field of the Invention
The present invention generally relates to digital signal processing, and more particularly to a device for decoding a series signal including a plurality of data pieces described by codes having variable code lengths to reproduce the original equi-length codes.
(2) Description of the Related Art
Variable-length coding is intended to enhance coding efficiency. For example, the CCITT Recommendation H.261 defines a variable-length code. In a conventional equi-length coding, data pieces are described by equi-length code words. In the variable-length coding, an event which frequently occurs is described by a short code word, and an event which does not frequently occur is described by a long code word. The average of the lengths of variable-length code words is smaller than the fixed length of equi-length code words. The variable-length coding as described above is widely used as an effective means for efficiently encoding video or image data.
In a system capable of transmitting the variable-length codes, only effective data pieces which may have different lengths are successively transmitted. On the receiver side, the effective data pieces are decoded in a decoding unit which consists of a predetermined number of consecutive bits, the most significant bit of which is the beginning bit of each of the effective data pieces. In this manner, equi-length codes are reproduced.
FIG. 1 is a block diagram of a conventional variable-length code decoding device. The device shown in FIG. 1 is composed of a S/P (Serial to Parallel) converter 1, a buffer memory 2, a barrel shifter 3, a code word decoder 4, a code length detector 5, a code length register 61, a shifted-number register 62, and a MOD(N) adder 7. Serial data transmitted via a transmission path interface port (not shown) is sequentially converted into parallel data for every N bits or every N-bit group (for example, one byte), and then stored in the buffer memory 2. This buffer memory 2 always stores 2 N-byte parallel data (two-byte parallel data) which consists of the previously received N-byte data and the N-byte data received at the present time. It is now assumed, for the sake of simplicity, that the buffer memory 2 always holds two bytes. The two-byte parallel data is always output from the buffer memory 2. When the buffer memory 2 receives a carry signal from the adder 7, the contents of the buffer memory 2 are updated so that it stores the current (latest) one-byte data and the next one-byte data. The barrel shifter 3, which is controlled by a shifted number "j" (the number of bits to be shifted), is formed with a bit shifter, and always inputs the two-byte parallel data from the buffer memory 2. The barrel shifter 3 shifts the two-byte parallel data by the shifted number "j" in a high-order-bit direction, and outputs data consisting of eight consecutive bits, the beginning bit of which is the (j+1)th bit from the most significant bit of the received two-byte parallel data. In this manner, the beginning bit of the effective data which is about to be processed by the code word decoder 4 is placed at the most significant bit of the one-byte parallel data output by the barrel shifter 3.
The code word decoder 4 is formed with a ROM (Read Only Memory), and receives, as an address signal, a bit pattern of the one-byte data output by the barrel shifter 3. A fixed-length code pattern specified by the bit pattern is read out from the code word decoder 4. The code length detector is formed with a ROM, which receives, as an address signal, the bit pattern output by the barrel shifter 3. The code length detector 5 stores various numbers of bits corresponding to various bit patterns. In response to the bit pattern from the barrel shifter 3, the number of bits (code length) which form the effective data from the barrel shifter 3 is output to the code length register 61. The effective data transmitted in the present system has a code length smaller than or equal to the number of bits N (one byte), and the last-bit position of the code is definitely determined by the pattern. Hence, it is possible to reproduce all fixed-length code words by storing all the fixed-length code words corresponding to all the possible code patterns in the code word decoder 4, and it is possible to detect the lengths of all effective data by storing the code lengths corresponding to all the possible code patterns.
The code-length data "m" output by the code length detector 5 is input to the adder 7 via the code length register 61. The register 62 holds the previous shifted number "j'", which is input to the adder 7. Then, the adder 7 executes a MOD(N) addition operation on the code length "m" and the previous shifted number "j'". The result of this addition is the updated shifted number "j".
A description will now be given of the operation of the variable-length code decoding device shown in FIG. 1. The code-length data m read out from the code length detector 5 is input to the code length register 61. The updated shifted number "j" output by the adder 7 is input to the register 62. Each of the registers 61 and 62 can be formed with a D-type flip-flop, which is driven by an operation clock signal CLK. After a predetermined operation delay time .alpha., the data m and j' are output from the registers 61 and 62, respectively, and input to the adder 7. After a predetermined operation delay time .beta., the result of the MOD(N) addition operation, "j", is output by the adder 7. If the result of the operation shows the number of bits smaller than N, j is equal to j'+m. If the result shows the number of bits equal to or larger than N, j is equal to j'+m-N, and a carry signal CRY is made active (that is, shows "1"). Since the shifted number is changed from "j'" to "j", the barrel shifter 3 shifts the two-byte parallel data by j bits, and outputs the shifted bits after a predetermined operation delay time .gamma.. When the carry signal CRY is generated, the input from the buffer memory 2 to the barrel shifter 3 is switched to 2 N bits obtained by shifting the currently stored 2 N bits by N bits in the high-order-bit direction. The barrel shifter 3 shifts the updated 2 N bits by the shifted number "j" in the manner as described above. After a predetermined operation delay time .delta., the code length data "m" of the bit pattern output by the barrel shifter 3 is output by the code length detector 5.
It should be noted that the above-mentioned decoding process should be carried out within one cycle of the operation clock signal CLK. It takes a time (delay time) .alpha.+.beta.+.gamma.+.delta. to calculate the shifted number "j" by a shifted number calculation loop. This delay time must be within one cycle of the operation clock signal CLK. Hence, the maximum frequency of the operation clock signal CLK is limited by the delay time necessary to obtain the shifted number "j".